35#include "asm/platform.h"
43 __asm__
volatile(
"mrc p15, 0, %0, c9, c12, 0" :
"=r"(value));
49 value &= ARMV7_PMNC_MASK;
50 __asm__
volatile(
"mcr p15, 0, %0, c9, c12, 0" : :
"r"(value));
56 return pmnc & ARMV7_OVERFLOWED_MASK;
61 return pmnc & ARMV7_CNT2BIT(ARMV7_IDX2CNT(index));
66 return index <= ARMV7_IDX_COUNTER_LAST;
71 UINT32 counter = ARMV7_IDX2CNT(index);
72 __asm__
volatile(
"mcr p15, 0, %0, c9, c12, 5" : :
"r" (counter));
79 PRINT_ERR(
"CPU writing wrong counter %u\n", index);
80 }
else if (index == ARMV7_IDX_CYCLE_COUNTER) {
81 __asm__
volatile(
"mcr p15, 0, %0, c9, c13, 0" : :
"r" (period));
84 __asm__
volatile(
"mcr p15, 0, %0, c9, c13, 2" : :
"r" (period));
90 PRINT_DEBUG(
"bind event: %u to counter: %u\n", value, index);
92 value &= ARMV7_EVTYPE_MASK;
93 __asm__
volatile(
"mcr p15, 0, %0, c9, c13, 1" : :
"r" (value));
98 UINT32 counter = ARMV7_IDX2CNT(index);
99 PRINT_DEBUG(
"index : %u, counter: %u\n", index, counter);
100 __asm__
volatile(
"mcr p15, 0, %0, c9, c12, 1" : :
"r" (ARMV7_CNT2BIT(counter)));
105 UINT32 counter = ARMV7_IDX2CNT(index);
106 PRINT_DEBUG(
"index : %u, counter: %u\n", index, counter);
107 __asm__
volatile(
"mcr p15, 0, %0, c9, c12, 2" : :
"r" (ARMV7_CNT2BIT(counter)));
112 UINT32 counter = ARMV7_IDX2CNT(index);
113 __asm__
volatile(
"mcr p15, 0, %0, c9, c14, 1" : :
"r" (ARMV7_CNT2BIT(counter)));
119 UINT32 counter = ARMV7_IDX2CNT(index);
120 __asm__
volatile(
"mcr p15, 0, %0, c9, c14, 2" : :
"r" (ARMV7_CNT2BIT(counter)));
122 __asm__
volatile(
"mcr p15, 0, %0, c9, c12, 3" : :
"r" (ARMV7_CNT2BIT(counter)));
130 __asm__
volatile(
"mrc p15, 0, %0, c9, c12, 3" :
"=r" (value));
131 value &= ARMV7_FLAG_MASK;
132 __asm__
volatile(
"mcr p15, 0, %0, c9, c12, 3" : :
"r" (value));
139 UINT32 cnt =
event->counter;
142 PRINT_ERR(
"CPU enabling wrong PMNC counter IRQ enable %u\n", cnt);
147 PRINT_INFO(
"event period value not valid, counter: %u\n", cnt);
163 if (cnt != ARMV7_IDX_CYCLE_COUNTER) {
172 PRINT_DEBUG(
"enabled event: %u cnt: %u\n", event->
eventId, cnt);
177 UINT32 cnt =
event->counter;
180 PRINT_ERR(
"CPU enabling wrong PMNC counter IRQ enable %u\n", cnt);
193 PRINT_DEBUG(
"starting pmu...\n");
200 reg &= ~ARMV7_PMNC_D;
209 PRINT_DEBUG(
"stopping pmu...\n");
221 for (index = ARMV7_IDX_CYCLE_COUNTER; index < ARMV7_IDX_MAX_COUNTER; index++) {
234 PRINT_INFO(
"counter: %u, period: 0x%x\n", event->
counter, event->
period);
242 UINT32 index =
event->counter;
245 PRINT_ERR(
"CPU reading wrong counter %u\n", index);
246 }
else if (index == ARMV7_IDX_CYCLE_COUNTER) {
247 __asm__
volatile(
"mrc p15, 0, %0, c9, c13, 0" :
"=r" (value));
250 __asm__
volatile(
"mrc p15, 0, %0, c9, c13, 2" :
"=r" (value));
253 if (value < PERIOD_CALC(event->
period)) {
255 value +=
event->period;
258 value -= PERIOD_CALC(event->
period);
283 for (i = 0; i < ARRAY_SIZE(
g_armv7Map); i++) {
288 return PERF_HW_INVALID_EVENT_TYPE;
311 for (index = 0; index < eventNum; index++) {
312 Event *
event = &(events->
per[index]);
331 return ARMV7_IDX_MAX_COUNTER;
336 return ARMV7_IDX_CYCLE_COUNTER;
341 return ARMV7_IDX_COUNTER0;
361 for (index = 0; index < LOSCFG_KERNEL_CORE_NUM; index++) {
364 PRINT_ERR(
"pmu %u irq handler register failed\n", g_pmuIrqNr[index]);
367#ifdef LOSCFG_KERNEL_SMP
STATIC VOID Armv7ResetAllCnt(VOID)
STATIC INLINE UINT32 Armv7PmuCntOverflowed(UINT32 pmnc, UINT32 index)
STATIC UINTPTR Armv7ReadEventCnt(Event *event)
STATIC INLINE UINT32 Armv7PmuOverflowed(UINT32 pmnc)
STATIC VOID Armv7SetEventPeriod(Event *event)
STATIC INLINE VOID Armv7EnableCnt(UINT32 index)
UINT32 OsGetPmuMaxCounter(VOID)
STATIC VOID Armv7DisableEvent(Event *event)
STATIC INLINE VOID Armv7EnableCntInterrupt(UINT32 index)
UINT32 OsGetPmuCounter0(VOID)
STATIC const UINT32 g_armv7Map[]
STATIC INLINE VOID Armv7PmuSetCntPeriod(UINT32 index, UINT32 period)
STATIC INLINE VOID Armv7BindEvt2Cnt(UINT32 index, UINT32 value)
STATIC INLINE VOID Armv7PmuSelCnt(UINT32 index)
STATIC VOID Armv7StartAllCnt(VOID)
UINT32 OsGetPmuCycleCounter(VOID)
STATIC INLINE UINT32 Armv7PmncRead(VOID)
UINT32 Armv7PmuMapEvent(UINT32 eventType, BOOL reverse)
STATIC INLINE UINT32 Armv7PmuGetOverflowStatus(VOID)
STATIC VOID Armv7StopAllCnt(VOID)
STATIC INLINE VOID Armv7PmncWrite(UINT32 value)
STATIC INLINE UINT32 Armv7CntValid(UINT32 index)
STATIC VOID Armv7PmuIrqHandler(VOID)
OS_PMU_INTS(LOSCFG_KERNEL_CORE_NUM, g_pmuIrqNr)
STATIC INLINE VOID Armv7DisableCnt(UINT32 index)
STATIC VOID Armv7EnableEvent(Event *event)
STATIC INLINE VOID Armv7DisableCntInterrupt(UINT32 index)
@ ARMV7_PERF_HW_DCACHE_MISSES
@ ARMV7_PERF_HW_BRANCE_MISSES
@ ARMV7_PERF_HW_INSTRUCTIONS
@ ARMV7_PERF_HW_ICACHE_MISSES
VOID HalIrqUnmask(UINT32 vector)
撤销中断屏蔽
VOID HalIrqMask(UINT32 vector)
屏蔽中断
VOID HalIrqSetAffinity(UINT32 vector, UINT32 cpuMask)
STATIC INLINE VOID LOS_IntRestore(UINT32 intSave)
Restore interrupts. | 恢复到使用LOS_IntLock关闭所有中断之前的状态
LITE_OS_SEC_TEXT_INIT UINT32 LOS_HwiCreate(HWI_HANDLE_T hwiNum, HWI_PRIOR_T hwiPrio, HWI_MODE_T hwiMode, HWI_PROC_FUNC hwiHandler, HwiIrqParam *irqParam)
创建一个硬中断 中断创建,注册中断号、中断触发模式、中断优先级、中断处理程序。中断被触发时, handleIrq会调用该中断处理程序
STATIC INLINE UINT32 LOS_IntLock(VOID)
Disable all interrupts. | 关闭当前处理器所有中断响应
@ PERF_COUNT_HW_BRANCH_INSTRUCTIONS
@ PERF_COUNT_HW_DCACHE_MISSES
@ PERF_COUNT_HW_DCACHE_REFERENCES
@ PERF_COUNT_HW_BRANCH_MISSES
@ PERF_COUNT_HW_ICACHE_MISSES
@ PERF_COUNT_HW_ICACHE_REFERENCES
@ PERF_COUNT_HW_CPU_CYCLES
@ PERF_COUNT_HW_INSTRUCTIONS
STATIC INLINE UINT32 ArchCurrCpuid(VOID)
VOID OsPerfHandleOverFlow(Event *event, PerfRegs *regs)
VOID OsPerfUpdateEventCount(Event *event, UINT32 value)
STATIC INLINE VOID OsPerfFetchIrqRegs(PerfRegs *regs)
UINT32 OsPerfHwInit(HwPmu *hwPmu)
Event per[PERF_MAX_EVENT]