39#ifdef LOSCFG_ARCH_GIC_V3
45 return ((MPIDR_AFF_LEVEL(mpidr, 3) << 32) |
46 (MPIDR_AFF_LEVEL(mpidr, 2) << 16) |
47 (MPIDR_AFF_LEVEL(mpidr, 1) << 8) |
48 (MPIDR_AFF_LEVEL(mpidr, 0)));
51#ifdef LOSCFG_KERNEL_SMP
57 while (next < LOSCFG_KERNEL_CORE_NUM) {
58 if (cpuMask & (1U << next)) {
74 UINT64 mpidr = CPU_MAP_GET(cpu);
75 while (cpu < LOSCFG_KERNEL_CORE_NUM) {
76 tList |= 1U << (mpidr & 0xf);
78 nextCpu =
NextCpu(cpu, cpuMask);
79 if (nextCpu >= LOSCFG_KERNEL_CORE_NUM) {
84 mpidr = CPU_MAP_GET(cpu);
85 if (cluster != (mpidr & ~0xffUL)) {
102 while (cpuMask && (cpu < LOSCFG_KERNEL_CORE_NUM)) {
103 if (cpuMask & (1U << cpu)) {
104 cluster = CPU_MAP_GET(cpu) & ~0xffUL;
109 val = ((MPIDR_AFF_LEVEL(cluster, 3) << 48) |
110 (MPIDR_AFF_LEVEL(cluster, 2) << 32) |
111 (MPIDR_AFF_LEVEL(cluster, 1) << 16) |
112 (irq << 24) | tList);
131 GIC_REG_64(GICD_IROUTER(irq)) = affinity;
138 INT32 count = 1000000;
140 while (GIC_REG_32(reg) & GICD_CTLR_RWP) {
143 PRINTK(
"gic_v3: rwp timeout 0x%x\n", GIC_REG_32(reg));
152#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
153 GIC_REG_32(GICD_IGROUPR(irq / 32)) = 0;
155 GIC_REG_32(GICD_IGROUPR(irq / 32)) = 0xffffffff;
161 GIC_REG_32(GICR_WAKER(cpu)) &= ~GICR_WAKER_PROCESSORSLEEP;
164 while ((GIC_REG_32(GICR_WAKER(cpu)) & 0x4) == GICR_WAKER_CHILDRENASLEEP);
170#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
171 GIC_REG_32(GICR_IGROUPR0(cpu)) = 0;
172 GIC_REG_32(GICR_IGRPMOD0(cpu)) = 0;
174 GIC_REG_32(GICR_IGROUPR0(cpu)) = 0xffffffff;
181 UINT32 newPri = GIC_REG_32(GICD_IPRIORITYR(pos));
184 newPri &= ~(GIC_PRIORITY_MASK << ((irq % 4) * GIC_PRIORITY_OFFSET));
185 newPri |= priority << ((irq % 4) * GIC_PRIORITY_OFFSET);
187 GIC_REG_32(GICD_IPRIORITYR(pos)) = newPri;
194 UINT32 newPri = GIC_REG_32(GICR_IPRIORITYR0(cpu) + pos * 4);
197 newPri &= ~(GIC_PRIORITY_MASK << ((irq % 4) * GIC_PRIORITY_OFFSET));
198 newPri |= priority << ((irq % 4) * GIC_PRIORITY_OFFSET);
200 GIC_REG_32(GICR_IPRIORITYR0(cpu) + pos * 4) = newPri;
216 LOS_ASSERT(sre & 0x1);
219#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
251 const UINT32 mask = 1U << (vector % 32);
253 if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
258 for (i = 0; i < LOSCFG_KERNEL_CORE_NUM; i++) {
259 GIC_REG_32(GICR_ICENABLER0(i)) = mask;
263 GIC_REG_32(GICD_ICENABLER(vector >> 5)) = mask;
271 const UINT32 mask = 1U << (vector % 32);
273 if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
278 for (i = 0; i < LOSCFG_KERNEL_CORE_NUM; i++) {
279 GIC_REG_32(GICR_ISENABLER0(i)) = mask;
283 GIC_REG_32(GICD_ISENABLER(vector >> 5)) = mask;
290 if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
294 GIC_REG_32(GICD_ISPENDR(vector >> 5)) = 1U << (vector % 32);
305 UINT8 prio = priority;
307 if (vector > OS_HWI_MAX_NUM) {
308 PRINT_ERR(
"Invalid irq value %u, max irq is %u\n", vector, OS_HWI_MAX_NUM);
312 prio = prio & (
UINT8)GIC_INTR_PRIO_MASK;
314 if (vector >= GIC_MIN_SPI_NUM) {
334 GIC_REG_32(GICR_ICENABLER0(cpu)) = 0xffffffff;
335 GIC_REG_32(GICR_ICPENDR0(cpu)) = 0xffffffff;
337 GIC_REG_32(GICR_ISENABLER0(cpu)) = 0xffffffff;
339 for (idx = 0; idx < GIC_MIN_SPI_NUM; idx += 1) {
348#ifdef LOSCFG_KERNEL_SMP
361 GIC_REG_32(GICD_CTLR) = 0;
366 for (i = 32; i < OS_HWI_MAX_NUM; i += 16) {
367 GIC_REG_32(GICD_ICFGR(i / 16)) = 0;
371 for (i = 32; i < OS_HWI_MAX_NUM; i += 32) {
372 GIC_REG_32(GICD_ICENABLER(i / 32)) = 0xffffffff;
373 GIC_REG_32(GICD_ICPENDR(i / 32)) = 0xffffffff;
374 GIC_REG_32(GICD_IGRPMODR(i / 32)) = 0;
380 for (i = 32; i < OS_HWI_MAX_NUM; i++) {
387 for (i = 0; i < OS_HWI_MAX_NUM; i += 32) {
388 GIC_REG_32(GICD_ICENABLER(i / 32)) = 0xffffffff;
392 GIC_REG_32(GICD_CTLR) = CTLR_ENALBE_G0 | CTLR_ENABLE_G1NS | CTLR_ARE_S;
396 for (i = 32; i < OS_HWI_MAX_NUM; i++) {
397 GIC_REG_64(GICD_IROUTER(i)) = affinity;
402#ifdef LOSCFG_KERNEL_SMP
407#ifdef LOSCFG_KERNEL_SMP_CALL
416 UINT32 vector = iar & 0x3FFU;
423 if (vector >= OS_HWI_MAX_NUM) {
434 UINT32 pidr = GIC_REG_32(GICD_PIDR2V3);
435 CHAR *irqVerString = NULL;
437 switch (pidr >> GIC_REV_OFFSET) {
439 irqVerString =
"GICv3";
442 irqVerString =
"GICv4";
445 irqVerString =
"unknown";
GIC(Generic Interrupt Controller)是ARM公司提供的一个通用的中断控制器 http://weharmonyos.com/blog/44....
UINT32 HalCurIrqGet(VOID)
获取当前中断号
VOID HalIrqInit(VOID)
中断控制器本身初始化
VOID HalIrqSendIpi(UINT32 target, UINT32 ipi)
STATIC INLINE VOID GicrSetWaker(UINT32 cpu)
STATIC VOID GicrSetPmr(UINT32 irq, UINT8 priority)
STATIC INLINE VOID GicdSetGroup(UINT32 irq)
STATIC INLINE VOID GicrSetGroup(UINT32 cpu)
VOID HalIrqUnmask(UINT32 vector)
撤销中断屏蔽
STATIC UINT32 NextCpu(UINT32 cpu, UINT32 cpuMask)
UINT32 HalIrqSetPrio(UINT32 vector, UINT8 priority)
STATIC VOID GiccInitPercpu(VOID)
VOID HalIrqPending(UINT32 vector)
VOID HalIrqSetAffinity(UINT32 irq, UINT32 cpuMask)
VOID HalIrqClear(UINT32 vector)
STATIC VOID GicSgi(UINT32 irq, UINT32 cpuMask)
STATIC UINT16 GicTargetList(UINT32 *base, UINT32 cpuMask, UINT64 cluster)
VOID HalIrqMask(UINT32 vector)
屏蔽中断
VOID HalIrqInitPercpu(VOID)
中断控制器与CPU之间的关系初始化
STATIC UINT32 g_curIrqNum
STATIC INLINE UINT64 MpidrToAffinity(UINT64 mpidr)
STATIC VOID GicdSetPmr(UINT32 irq, UINT8 priority)
STATIC VOID GicWaitForRwp(UINT64 reg)
CHAR * HalIrqVersion(VOID)
STATIC INLINE VOID GiccSetBpr0(UINT32 val)
STATIC INLINE VOID GiccSetCtlr(UINT32 val)
STATIC INLINE VOID GiccSetIgrpen1(UINT32 val)
STATIC INLINE UINT32 GiccGetSre(VOID)
STATIC INLINE UINT32 GiccGetIar(VOID)
STATIC INLINE VOID GiccSetEoir(UINT32 val)
STATIC INLINE VOID GiccSetPmr(UINT32 val)
STATIC INLINE VOID GiccSetSgi1r(UINT64 val)
STATIC INLINE VOID GiccSetIgrpen0(UINT32 val)
STATIC INLINE VOID GiccSetSre(UINT32 val)
LITE_OS_SEC_TEXT_INIT UINT32 LOS_HwiCreate(HWI_HANDLE_T hwiNum, HWI_PRIOR_T hwiPrio, HWI_MODE_T hwiMode, HWI_PROC_FUNC hwiHandler, HwiIrqParam *irqParam)
创建一个硬中断 中断创建,注册中断号、中断触发模式、中断优先级、中断处理程序。中断被触发时, handleIrq会调用该中断处理程序
STATIC INLINE UINT32 ArchCurrCpuid(VOID)
VOID OsInterrupt(UINT32 intNum)
VOID OsMpWakeHandler(VOID)
硬中断唤醒处理函数
VOID OsMpFuncCallHandler(VOID)
OsMpFuncCallHandler 回调向当前CPU注册过的函数
VOID OsMpScheduleHandler(VOID)
硬中断调度处理函数
@ LOS_MP_IPI_SCHEDULE
!< 唤醒CPU
@ LOS_MP_IPI_FUNC_CALL
!< 停止CPU
@ LOS_MP_IPI_HALT
!< 调度CPU