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更新日期: 2022/06/01 来源: https://gitee.com/weharmony/kernel_liteos_a_note
los_mmu_descriptor_v6.h
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/*
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* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
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* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list
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* of conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @defgroup los_mmu_descriptor_v6 MMU Descriptor v6
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* @ingroup kernel
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*/
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#ifndef __LOS_MMU_DESCRIPTOR_V6_H__
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#define __LOS_MMU_DESCRIPTOR_V6_H__
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#include "
los_vm_common.h
"
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#ifdef __cplusplus
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#if __cplusplus
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extern
"C"
{
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#endif
/* __cplusplus */
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#endif
/* __cplusplus */
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#define __iomem
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#ifndef IS_ALIGNED
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#define IS_ALIGNED(a, b) (!(((UINTPTR)(a)) & (((UINTPTR)(b))-1)))
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#endif
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#define MMU_DESCRIPTOR_TEX_0 0
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#define MMU_DESCRIPTOR_TEX_1 1
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#define MMU_DESCRIPTOR_TEX_2 2
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#define MMU_DESCRIPTOR_TEX_MASK 7
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#define MMU_DESCRIPTOR_CACHE_BUFFER_SHIFT 2
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#define MMU_DESCRIPTOR_CACHE_BUFFER(x) ((x) << MMU_DESCRIPTOR_CACHE_BUFFER_SHIFT)
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#define MMU_DESCRIPTOR_NON_CACHEABLE MMU_DESCRIPTOR_CACHE_BUFFER(0)
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#define MMU_DESCRIPTOR_WRITE_BACK_ALLOCATE MMU_DESCRIPTOR_CACHE_BUFFER(1)
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#define MMU_DESCRIPTOR_WRITE_THROUGH_NO_ALLOCATE MMU_DESCRIPTOR_CACHE_BUFFER(2)
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#define MMU_DESCRIPTOR_WRITE_BACK_NO_ALLOCATE MMU_DESCRIPTOR_CACHE_BUFFER(3)
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/* user space mmu access permission define begin */
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#define MMU_DESCRIPTOR_DOMAIN_MANAGER 0
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#define MMU_DESCRIPTOR_DOMAIN_CLIENT 1
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#define MMU_DESCRIPTOR_DOMAIN_NA 2
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/* L1 descriptor type */
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#define MMU_DESCRIPTOR_L1_TYPE_INVALID (0x0 << 0)
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#define MMU_DESCRIPTOR_L1_TYPE_PAGE_TABLE (0x1 << 0)
///< 一级条目类型按页分
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#define MMU_DESCRIPTOR_L1_TYPE_SECTION (0x2 << 0)
///< 1MB 一级条目类型按段分
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#define MMU_DESCRIPTOR_L1_TYPE_MASK (0x3 << 0)
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/* L2 descriptor type */
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#define MMU_DESCRIPTOR_L2_TYPE_INVALID (0x0 << 0)
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#define MMU_DESCRIPTOR_L2_TYPE_LARGE_PAGE (0x1 << 0)
///< 64KB 二级条目类型按大页分
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#define MMU_DESCRIPTOR_L2_TYPE_SMALL_PAGE (0x2 << 0)
///< 4KB 二级条目类型按小页分
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#define MMU_DESCRIPTOR_L2_TYPE_SMALL_PAGE_XN (0x3 << 0)
///< 1KB 二级条目类型按极小页分
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#define MMU_DESCRIPTOR_L2_TYPE_MASK (0x3 << 0)
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#define MMU_DESCRIPTOR_IS_L1_SIZE_ALIGNED(x) IS_ALIGNED(x, MMU_DESCRIPTOR_L1_SMALL_SIZE)
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#define MMU_DESCRIPTOR_L1_SMALL_SIZE 0x100000
// 1M 页表L1大小
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#define MMU_DESCRIPTOR_L1_SMALL_MASK (MMU_DESCRIPTOR_L1_SMALL_SIZE - 1)
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#define MMU_DESCRIPTOR_L1_SMALL_FRAME (~MMU_DESCRIPTOR_L1_SMALL_MASK)
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#define MMU_DESCRIPTOR_L1_SMALL_SHIFT 20
//移动位数
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#define MMU_DESCRIPTOR_L1_SECTION_ADDR(x) ((x) & MMU_DESCRIPTOR_L1_SMALL_FRAME)
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#define MMU_DESCRIPTOR_L1_PAGE_TABLE_ADDR(x) ((x) & ~((1 << 10)-1))
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#define MMU_DESCRIPTOR_L1_SMALL_L2_TABLES_PER_PAGE 4
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#define MMU_DESCRIPTOR_L1_SMALL_ENTRY_NUMBERS 0x4000U
///< 页表必须按16Kb对齐,因为C2寄存器低14位为0
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#define MMU_DESCRIPTOR_L1_SMALL_DOMAIN_MASK (~(0x0f << 5))
/* 4k page section domain mask */
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#define MMU_DESCRIPTOR_L1_SMALL_DOMAIN_CLIENT (MMU_DESCRIPTOR_DOMAIN_CLIENT << 5)
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#define MMU_DESCRIPTOR_L1_PAGETABLE_NON_SECURE (1 << 3)
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#define MMU_DESCRIPTOR_L1_SECTION_NON_SECURE (1 << 19)
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#define MMU_DESCRIPTOR_L1_SECTION_SHAREABLE (1 << 16)
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#define MMU_DESCRIPTOR_L1_SECTION_NON_GLOBAL (1 << 17)
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#define MMU_DESCRIPTOR_L1_SECTION_XN (1 << 4)
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/* TEX CB */
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#define MMU_DESCRIPTOR_L1_TEX_SHIFT 12
/* type extension field shift */
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#define MMU_DESCRIPTOR_L1_TEX(x) \
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((x) << MMU_DESCRIPTOR_L1_TEX_SHIFT)
/* type extension */
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#define MMU_DESCRIPTOR_L1_TYPE_STRONGLY_ORDERED \
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(MMU_DESCRIPTOR_L1_TEX(MMU_DESCRIPTOR_TEX_0) | MMU_DESCRIPTOR_NON_CACHEABLE)
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#define MMU_DESCRIPTOR_L1_TYPE_NORMAL_NOCACHE \
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(MMU_DESCRIPTOR_L1_TEX(MMU_DESCRIPTOR_TEX_1) | MMU_DESCRIPTOR_NON_CACHEABLE)
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#define MMU_DESCRIPTOR_L1_TYPE_DEVICE_SHARED \
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(MMU_DESCRIPTOR_L1_TEX(MMU_DESCRIPTOR_TEX_0) | MMU_DESCRIPTOR_WRITE_BACK_ALLOCATE)
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#define MMU_DESCRIPTOR_L1_TYPE_DEVICE_NON_SHARED \
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(MMU_DESCRIPTOR_L1_TEX(MMU_DESCRIPTOR_TEX_2) | MMU_DESCRIPTOR_NON_CACHEABLE)
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#define MMU_DESCRIPTOR_L1_TYPE_NORMAL_WRITE_BACK_ALLOCATE \
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(MMU_DESCRIPTOR_L1_TEX(MMU_DESCRIPTOR_TEX_1) | MMU_DESCRIPTOR_WRITE_BACK_NO_ALLOCATE)
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#define MMU_DESCRIPTOR_L1_TEX_TYPE_MASK \
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(MMU_DESCRIPTOR_L1_TEX(MMU_DESCRIPTOR_TEX_MASK) | MMU_DESCRIPTOR_WRITE_BACK_NO_ALLOCATE)
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#define MMU_DESCRIPTOR_L1_AP2_SHIFT 15
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#define MMU_DESCRIPTOR_L1_AP2(x) ((x) << MMU_DESCRIPTOR_L1_AP2_SHIFT)
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#define MMU_DESCRIPTOR_L1_AP2_0 (MMU_DESCRIPTOR_L1_AP2(0))
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#define MMU_DESCRIPTOR_L1_AP2_1 (MMU_DESCRIPTOR_L1_AP2(1))
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#define MMU_DESCRIPTOR_L1_AP01_SHIFT 10
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#define MMU_DESCRIPTOR_L1_AP01(x) ((x) << MMU_DESCRIPTOR_L1_AP01_SHIFT)
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#define MMU_DESCRIPTOR_L1_AP01_0 (MMU_DESCRIPTOR_L1_AP01(0))
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#define MMU_DESCRIPTOR_L1_AP01_1 (MMU_DESCRIPTOR_L1_AP01(1))
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#define MMU_DESCRIPTOR_L1_AP01_3 (MMU_DESCRIPTOR_L1_AP01(3))
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#define MMU_DESCRIPTOR_L1_AP_P_NA_U_NA (MMU_DESCRIPTOR_L1_AP2_0 | MMU_DESCRIPTOR_L1_AP01_0)
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#define MMU_DESCRIPTOR_L1_AP_P_RW_U_RW (MMU_DESCRIPTOR_L1_AP2_0 | MMU_DESCRIPTOR_L1_AP01_3)
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#define MMU_DESCRIPTOR_L1_AP_P_RW_U_NA (MMU_DESCRIPTOR_L1_AP2_0 | MMU_DESCRIPTOR_L1_AP01_1)
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#define MMU_DESCRIPTOR_L1_AP_P_RO_U_RO (MMU_DESCRIPTOR_L1_AP2_1 | MMU_DESCRIPTOR_L1_AP01_3)
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#define MMU_DESCRIPTOR_L1_AP_P_RO_U_NA (MMU_DESCRIPTOR_L1_AP2_1 | MMU_DESCRIPTOR_L1_AP01_1)
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#define MMU_DESCRIPTOR_L1_AP_MASK (MMU_DESCRIPTOR_L1_AP2_1 | MMU_DESCRIPTOR_L1_AP01_3)
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#define MMU_DESCRIPTOR_L2_SMALL_SIZE 0x1000
// L2 小页大小 4K
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#define MMU_DESCRIPTOR_L2_SMALL_MASK (MMU_DESCRIPTOR_L2_SMALL_SIZE - 1)
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#define MMU_DESCRIPTOR_L2_SMALL_FRAME (~MMU_DESCRIPTOR_L2_SMALL_MASK)
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#define MMU_DESCRIPTOR_L2_SMALL_SHIFT 12
//小页偏移 12位
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#define MMU_DESCRIPTOR_L2_NUMBERS_PER_L1 \
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(MMU_DESCRIPTOR_L1_SMALL_SIZE >> MMU_DESCRIPTOR_L2_SMALL_SHIFT)
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#define MMU_DESCRIPTOR_IS_L2_SIZE_ALIGNED(x) IS_ALIGNED(x, MMU_DESCRIPTOR_L2_SMALL_SIZE)
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#define MMU_DESCRIPTOR_L2_TEX_SHIFT 6
/* type extension field shift */
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#define MMU_DESCRIPTOR_L2_TEX(x) \
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((x) << MMU_DESCRIPTOR_L2_TEX_SHIFT)
/* type extension */
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#define MMU_DESCRIPTOR_L2_TYPE_STRONGLY_ORDERED \
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(MMU_DESCRIPTOR_L2_TEX(MMU_DESCRIPTOR_TEX_0) | MMU_DESCRIPTOR_NON_CACHEABLE)
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#define MMU_DESCRIPTOR_L2_TYPE_NORMAL_NOCACHE \
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(MMU_DESCRIPTOR_L2_TEX(MMU_DESCRIPTOR_TEX_1) | MMU_DESCRIPTOR_NON_CACHEABLE)
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#define MMU_DESCRIPTOR_L2_TYPE_DEVICE_SHARED \
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(MMU_DESCRIPTOR_L2_TEX(MMU_DESCRIPTOR_TEX_0) | MMU_DESCRIPTOR_WRITE_BACK_ALLOCATE)
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#define MMU_DESCRIPTOR_L2_TYPE_DEVICE_NON_SHARED \
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(MMU_DESCRIPTOR_L2_TEX(MMU_DESCRIPTOR_TEX_2) | MMU_DESCRIPTOR_NON_CACHEABLE)
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#define MMU_DESCRIPTOR_L2_TYPE_NORMAL_WRITE_BACK_ALLOCATE \
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(MMU_DESCRIPTOR_L2_TEX(MMU_DESCRIPTOR_TEX_1) | MMU_DESCRIPTOR_WRITE_BACK_NO_ALLOCATE)
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#define MMU_DESCRIPTOR_L2_TEX_TYPE_MASK \
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(MMU_DESCRIPTOR_L2_TEX(MMU_DESCRIPTOR_TEX_MASK) | MMU_DESCRIPTOR_WRITE_BACK_NO_ALLOCATE)
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#define MMU_DESCRIPTOR_L2_AP2_SHIFT 9
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#define MMU_DESCRIPTOR_L2_AP2(x) ((x) << MMU_DESCRIPTOR_L2_AP2_SHIFT)
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#define MMU_DESCRIPTOR_L2_AP2_0 (MMU_DESCRIPTOR_L2_AP2(0))
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#define MMU_DESCRIPTOR_L2_AP2_1 (MMU_DESCRIPTOR_L2_AP2(1))
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#define MMU_DESCRIPTOR_L2_AP01_SHIFT 4
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#define MMU_DESCRIPTOR_L2_AP01(x) ((x) << MMU_DESCRIPTOR_L2_AP01_SHIFT)
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#define MMU_DESCRIPTOR_L2_AP01_0 (MMU_DESCRIPTOR_L2_AP01(0))
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#define MMU_DESCRIPTOR_L2_AP01_1 (MMU_DESCRIPTOR_L2_AP01(1))
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#define MMU_DESCRIPTOR_L2_AP01_3 (MMU_DESCRIPTOR_L2_AP01(3))
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#define MMU_DESCRIPTOR_L2_AP_P_NA_U_NA (MMU_DESCRIPTOR_L2_AP2_0 | MMU_DESCRIPTOR_L2_AP01_0)
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#define MMU_DESCRIPTOR_L2_AP_P_RW_U_RW (MMU_DESCRIPTOR_L2_AP2_0 | MMU_DESCRIPTOR_L2_AP01_3)
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#define MMU_DESCRIPTOR_L2_AP_P_RW_U_NA (MMU_DESCRIPTOR_L2_AP2_0 | MMU_DESCRIPTOR_L2_AP01_1)
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#define MMU_DESCRIPTOR_L2_AP_P_RO_U_RO (MMU_DESCRIPTOR_L2_AP2_1 | MMU_DESCRIPTOR_L2_AP01_3)
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#define MMU_DESCRIPTOR_L2_AP_P_RO_U_NA (MMU_DESCRIPTOR_L2_AP2_1 | MMU_DESCRIPTOR_L2_AP01_1)
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#define MMU_DESCRIPTOR_L2_AP_MASK (MMU_DESCRIPTOR_L2_AP2_1 | MMU_DESCRIPTOR_L2_AP01_3)
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#define MMU_DESCRIPTOR_L2_SHAREABLE (1 << 10)
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#define MMU_DESCRIPTOR_L2_NON_GLOBAL (1 << 11)
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#define MMU_DESCRIPTOR_L2_SMALL_PAGE_ADDR(x) ((x) & MMU_DESCRIPTOR_L2_SMALL_FRAME)
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#define MMU_DESCRIPTOR_TTBCR_PD0 (1 << 4)
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#define MMU_DESCRIPTOR_TTBR_WRITE_BACK_ALLOCATE 1
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#define MMU_DESCRIPTOR_TTBR_RGN(x) (((x) & 0x3) << 3)
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#define MMU_DESCRIPTOR_TTBR_IRGN(x) ((((x) & 0x1) << 6) | ((((x) >> 1) & 0x1) << 0))
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#define MMU_DESCRIPTOR_TTBR_S (1 << 1)
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#define MMU_DESCRIPTOR_TTBR_NOS (1 << 5)
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#ifdef LOSCFG_KERNEL_SMP
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#define MMU_TTBRx_SHARABLE_FLAGS (MMU_DESCRIPTOR_TTBR_S | MMU_DESCRIPTOR_TTBR_NOS)
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#else
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#define MMU_TTBRx_SHARABLE_FLAGS 0
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#endif
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#define MMU_TTBRx_FLAGS \
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(MMU_DESCRIPTOR_TTBR_RGN(MMU_DESCRIPTOR_TTBR_WRITE_BACK_ALLOCATE) | \
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MMU_DESCRIPTOR_TTBR_IRGN(MMU_DESCRIPTOR_TTBR_WRITE_BACK_ALLOCATE) | \
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MMU_TTBRx_SHARABLE_FLAGS)
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#ifdef LOSCFG_KERNEL_SMP
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#define MMU_DESCRIPTOR_KERNEL_L1_PTE_FLAGS \
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(MMU_DESCRIPTOR_L1_TYPE_SECTION | \
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MMU_DESCRIPTOR_L1_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
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MMU_DESCRIPTOR_L1_AP_P_RW_U_NA | \
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MMU_DESCRIPTOR_L1_SMALL_DOMAIN_CLIENT | \
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MMU_DESCRIPTOR_L1_SECTION_SHAREABLE)
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#else
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#define MMU_DESCRIPTOR_KERNEL_L1_PTE_FLAGS \
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(MMU_DESCRIPTOR_L1_TYPE_SECTION | \
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MMU_DESCRIPTOR_L1_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
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MMU_DESCRIPTOR_L1_SMALL_DOMAIN_CLIENT | \
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MMU_DESCRIPTOR_L1_AP_P_RW_U_NA)
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#endif
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#define MMU_INITIAL_MAP_STRONGLY_ORDERED \
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(MMU_DESCRIPTOR_L1_TYPE_SECTION | \
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MMU_DESCRIPTOR_L1_TYPE_STRONGLY_ORDERED | \
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MMU_DESCRIPTOR_L1_SMALL_DOMAIN_CLIENT | \
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MMU_DESCRIPTOR_L1_AP_P_RW_U_NA)
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#define MMU_INITIAL_MAP_NORMAL_NOCACHE \
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(MMU_DESCRIPTOR_L1_TYPE_SECTION | \
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MMU_DESCRIPTOR_L1_TYPE_NORMAL_NOCACHE | \
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MMU_DESCRIPTOR_L1_SMALL_DOMAIN_CLIENT | \
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MMU_DESCRIPTOR_L1_AP_P_RW_U_NA)
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#define MMU_INITIAL_MAP_DEVICE \
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(MMU_DESCRIPTOR_L1_TYPE_SECTION | \
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MMU_DESCRIPTOR_L1_TYPE_DEVICE_SHARED | \
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MMU_DESCRIPTOR_L1_SMALL_DOMAIN_CLIENT | \
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MMU_DESCRIPTOR_L1_AP_P_RW_U_NA)
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#ifdef __cplusplus
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#if __cplusplus
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}
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#endif
/* __cplusplus */
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#endif
/* __cplusplus */
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#endif
/* __LOS_MMU_DESCRIPTOR_V6_H__ */
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los_vm_common.h
arch
arm
arm
include
los_mmu_descriptor_v6.h
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