枚举
enum	PmuEventType { ARMV7_PERF_HW_CYCLES = 0xFF , ARMV7_PERF_HW_INSTRUCTIONS = 0x08 , ARMV7_PERF_HW_DCACHES = 0x04 , ARMV7_PERF_HW_DCACHE_MISSES = 0x03 , ARMV7_PERF_HW_ICACHES = 0x14 , ARMV7_PERF_HW_ICACHE_MISSES = 0x01 , ARMV7_PERF_HW_BRANCHES = 0x0C , ARMV7_PERF_HW_BRANCE_MISSES = 0x10 , ARMV7_PERF_HW_PRED_BRANCH = 0x12 , ARMV7_PERF_HW_NUM_CYC_IRQ = 0x50 , ARMV7_PERF_HW_EXC_TAKEN = 0x09 , ARMV7_PERF_HW_DATA_READ = 0x06 , ARMV7_PERF_HW_DATA_WRITE = 0x07 , ARMV7_PERF_HW_STREX_PASSED = 0x80 , ARMV7_PERF_HW_STREX_FAILED = 0x81 , ARMV7_PERF_HW_LP_IN_TCM = 0x82 , ARMV7_PERF_HW_DMB_STALL = 0x90 , ARMV7_PERF_HW_ITCM_ACCESS = 0x91 , ARMV7_PERF_HW_DTCM_ACCESS = 0x92 , ARMV7_PERF_HW_DATA_EVICTION = 0x93 , ARMV7_PERF_HW_SCU = 0x94 , ARMV7_PERF_HW_INSCACHE_DEP_DW = 0x95 , ARMV7_PERF_HW_DATA_CACHE_DEP_STALL = 0x96 , ARMV7_PERF_HW_NOCACHE_NO_PER_DEP_STALL = 0x97 , ARMV7_PERF_HW_NOCACHE_PER_DEP_STALL = 0x98 , ARMV7_PERF_HW_DATA_CACHE_HP_DEP_STALL = 0x99 , ARMV7_PERF_HW_AXI_FAST_PERIPHERAL = 0x9A }

枚举类型说明

◆ PmuEventType

enum PmuEventType

枚举值
ARMV7_PERF_HW_CYCLES
ARMV7_PERF_HW_INSTRUCTIONS
ARMV7_PERF_HW_DCACHES
ARMV7_PERF_HW_DCACHE_MISSES
ARMV7_PERF_HW_ICACHES
ARMV7_PERF_HW_ICACHE_MISSES
ARMV7_PERF_HW_BRANCHES
ARMV7_PERF_HW_BRANCE_MISSES
ARMV7_PERF_HW_PRED_BRANCH
ARMV7_PERF_HW_NUM_CYC_IRQ
ARMV7_PERF_HW_EXC_TAKEN
ARMV7_PERF_HW_DATA_READ
ARMV7_PERF_HW_DATA_WRITE
ARMV7_PERF_HW_STREX_PASSED
ARMV7_PERF_HW_STREX_FAILED
ARMV7_PERF_HW_LP_IN_TCM
ARMV7_PERF_HW_DMB_STALL
ARMV7_PERF_HW_ITCM_ACCESS
ARMV7_PERF_HW_DTCM_ACCESS
ARMV7_PERF_HW_DATA_EVICTION
ARMV7_PERF_HW_SCU
ARMV7_PERF_HW_INSCACHE_DEP_DW
ARMV7_PERF_HW_DATA_CACHE_DEP_STALL
ARMV7_PERF_HW_NOCACHE_NO_PER_DEP_STALL
ARMV7_PERF_HW_NOCACHE_PER_DEP_STALL
ARMV7_PERF_HW_DATA_CACHE_HP_DEP_STALL
ARMV7_PERF_HW_AXI_FAST_PERIPHERAL

在文件 armv7_pmu_pri.h 第 72 行定义.

                  {
    ARMV7_PERF_HW_CYCLES                   = 0xFF,    /* cycles */
    ARMV7_PERF_HW_INSTRUCTIONS             = 0x08,    /* instructions */
    ARMV7_PERF_HW_DCACHES                  = 0x04,    /* dcache */
    ARMV7_PERF_HW_DCACHE_MISSES            = 0x03,    /* dcache-misses */
    ARMV7_PERF_HW_ICACHES                  = 0x14,    /* icache */
    ARMV7_PERF_HW_ICACHE_MISSES            = 0x01,    /* icache-misses */
    ARMV7_PERF_HW_BRANCHES                 = 0x0C,    /* software change of pc */
    ARMV7_PERF_HW_BRANCE_MISSES            = 0x10,    /* branch-misses */
    ARMV7_PERF_HW_PRED_BRANCH              = 0x12,    /* predictable branches */
    ARMV7_PERF_HW_NUM_CYC_IRQ              = 0x50,    /* number of cycles Irqs are interrupted */
    ARMV7_PERF_HW_EXC_TAKEN                = 0x09,    /* exception_taken */
    ARMV7_PERF_HW_DATA_READ                = 0x06,    /* data read */
    ARMV7_PERF_HW_DATA_WRITE               = 0x07,    /* data write */
    ARMV7_PERF_HW_STREX_PASSED             = 0x80,    /* strex passed */
    ARMV7_PERF_HW_STREX_FAILED             = 0x81,    /* strex failed */
    ARMV7_PERF_HW_LP_IN_TCM                = 0x82,    /* literal pool in TCM region */
    ARMV7_PERF_HW_DMB_STALL                = 0x90,    /* DMB stall */
    ARMV7_PERF_HW_ITCM_ACCESS              = 0x91,    /* ITCM access */
    ARMV7_PERF_HW_DTCM_ACCESS              = 0x92,    /* DTCM access */
    ARMV7_PERF_HW_DATA_EVICTION            = 0x93,    /* data eviction */
    ARMV7_PERF_HW_SCU                      = 0x94,    /* SCU coherency operation */
    ARMV7_PERF_HW_INSCACHE_DEP_DW          = 0x95,    /* instruction cache dependent stall */
    ARMV7_PERF_HW_DATA_CACHE_DEP_STALL     = 0x96,    /* data cache dependent stall */
    ARMV7_PERF_HW_NOCACHE_NO_PER_DEP_STALL = 0x97,    /* non-cacheable no peripheral dependent stall */
    ARMV7_PERF_HW_NOCACHE_PER_DEP_STALL    = 0x98,    /* non-Cacheable peripheral dependent stall */
    ARMV7_PERF_HW_DATA_CACHE_HP_DEP_STALL  = 0x99,    /* data cache high priority dependent stall */
    ARMV7_PERF_HW_AXI_FAST_PERIPHERAL      = 0x9A,    /* Accesses_to_AXI_fast_peripheral_port(reads_and_writes) */
};