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更新日期: 2022/06/01 来源: https://gitee.com/weharmony/kernel_liteos_a_note
gic_common.h
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/*!
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* @file gic_common.h
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* @brief GIC(Generic Interrupt Controller)是ARM公司提供的一个通用的中断控制器
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* @link http://weharmonyos.com/blog/44.html
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* @verbatim
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* @endverbatim
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* @version
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* @author weharmonyos.com | 鸿蒙研究站 | 每天死磕一点点
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* @date 2021-11-18
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*
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* @history
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*
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*/
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/*
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* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
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* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list
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* of conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _GIC_COMMON_H
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#define _GIC_COMMON_H
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#include "stdint.h"
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#include "target_config.h"
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#include "
los_config.h
"
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/* gic arch revision | GIC架构版本*/
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enum
{
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GICV1
= 1,
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GICV2
,
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GICV3
,
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GICV4
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};
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#define GIC_REV_MASK 0xF0
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#define GIC_REV_OFFSET 0x4
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/// 前往 http://weharmonyos.com 下载 对应datasheet
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#ifdef LOSCFG_ARCH_GIC_V2
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#define GICC_CTLR (GICC_OFFSET + 0x00)
/* CPU Interface Control Register | 控制寄存器,控制是否上报中断到处理器 */
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#define GICC_PMR (GICC_OFFSET + 0x04)
/* Interrupt Priority Mask Register | 中断优先级屏蔽寄存器*/
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#define GICC_BPR (GICC_OFFSET + 0x08)
/* Binary Point Register */
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#define GICC_IAR (GICC_OFFSET + 0x0c)
/* Interrupt Acknowledge Register | 中断回应寄存器,处理器会读取此寄存器,用来获取上报的中断号*/
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#define GICC_EOIR (GICC_OFFSET + 0x10)
/* End of Interrupt Register | 处理器会写这个寄存器来告知CPU interface,此中断已经处理完成*/
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#define GICC_RPR (GICC_OFFSET + 0x14)
/* Running Priority Register | 运行优先级寄存器,此寄存器的值表示当前CPU interface的运行优先级*/
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#define GICC_HPPIR (GICC_OFFSET + 0x18)
/* Highest Priority Pending Interrupt Register | 当前pending状态的最高优先级中断号,当在允许中断抢占的情况下,如果此中断的优先级值大于运行优先级寄存器的值的话,就会发生中断抢占*/
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#endif
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#define GICD_CTLR (GICD_OFFSET + 0x000)
/* Distributor Control Register */
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#define GICD_TYPER (GICD_OFFSET + 0x004)
/* Interrupt Controller Type Register */
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#define GICD_IIDR (GICD_OFFSET + 0x008)
/* Distributor Implementer Identification Register */
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#define GICD_IGROUPR(n) (GICD_OFFSET + 0x080 + (n) * 4)
/* Interrupt Group Registers */
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#define GICD_ISENABLER(n) (GICD_OFFSET + 0x100 + (n) * 4)
/* Interrupt Set-Enable Registers */
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#define GICD_ICENABLER(n) (GICD_OFFSET + 0x180 + (n) * 4)
/* Interrupt Clear-Enable Registers */
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#define GICD_ISPENDR(n) (GICD_OFFSET + 0x200 + (n) * 4)
/* Interrupt Set-Pending Registers */
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#define GICD_ICPENDR(n) (GICD_OFFSET + 0x280 + (n) * 4)
/* Interrupt Clear-Pending Registers */
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#define GICD_ISACTIVER(n) (GICD_OFFSET + 0x300 + (n) * 4)
/* GICv2 Interrupt Set-Active Registers */
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#define GICD_ICACTIVER(n) (GICD_OFFSET + 0x380 + (n) * 4)
/* Interrupt Clear-Active Registers */
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#define GICD_IPRIORITYR(n) (GICD_OFFSET + 0x400 + (n) * 4)
/* Interrupt Priority Registers */
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#define GICD_ITARGETSR(n) (GICD_OFFSET + 0x800 + (n) * 4)
/* Interrupt Processor Targets Registers */
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#define GICD_ICFGR(n) (GICD_OFFSET + 0xc00 + (n) * 4)
/* Interrupt Configuration Registers */
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#define GICD_SGIR (GICD_OFFSET + 0xf00)
/* Software Generated Interrupt Register */
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#define GICD_CPENDSGIR(n) (GICD_OFFSET + 0xf10 + (n) * 4)
/* SGI Clear-Pending Registers; NOT available on cortex-a9 */
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#define GICD_SPENDSGIR(n) (GICD_OFFSET + 0xf20 + (n) * 4)
/* SGI Set-Pending Registers; NOT available on cortex-a9 */
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#define GICD_PIDR2V2 (GICD_OFFSET + 0xfe8)
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#define GICD_PIDR2V3 (GICD_OFFSET + 0xffe8)
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#ifdef LOSCFG_ARCH_GIC_V3
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#define GICD_IGRPMODR(n) (GICD_OFFSET + 0x0d00 + (n) * 4)
/* Interrupt Group Mode Reisters */
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#define GICD_IROUTER(n) (GICD_OFFSET + 0x6000 + (n) * 8)
/* Interrupt Rounter Reisters */
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#endif
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#define GIC_REG_8(reg) (*(volatile UINT8 *)((UINTPTR)(GIC_BASE_ADDR + (reg))))
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#define GIC_REG_32(reg) (*(volatile UINT32 *)((UINTPTR)(GIC_BASE_ADDR + (reg))))
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#define GIC_REG_64(reg) (*(volatile UINT64 *)((UINTPTR)(GIC_BASE_ADDR + (reg))))
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#define GICD_INT_DEF_PRI 0xa0U
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#define GICD_INT_DEF_PRI_X4 (((UINT32)GICD_INT_DEF_PRI << 24) | \
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((UINT32)GICD_INT_DEF_PRI << 16) | \
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((UINT32)GICD_INT_DEF_PRI << 8) | \
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(UINT32)GICD_INT_DEF_PRI)
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#define GIC_MIN_SPI_NUM 32
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/* Interrupt preemption config */
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#define GIC_PRIORITY_MASK 0xFFU
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#define GIC_PRIORITY_OFFSET 8
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/*
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* The number of bits to shift for an interrupt priority is dependent
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* on the number of bits implemented by the interrupt controller.
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* If the MAX_BINARY_POINT_VALUE is 7,
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* it means that interrupt preemption is not supported.
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*/
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#ifndef LOSCFG_ARCH_INTERRUPT_PREEMPTION
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#define MAX_BINARY_POINT_VALUE 7
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#define PRIORITY_SHIFT 0
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#define GIC_MAX_INTERRUPT_PREEMPTION_LEVEL 0U
///< 中断最高优先级
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#else
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#define PRIORITY_SHIFT ((MAX_BINARY_POINT_VALUE + 1) % GIC_PRIORITY_OFFSET)
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#define GIC_MAX_INTERRUPT_PREEMPTION_LEVEL ((UINT8)((GIC_PRIORITY_MASK + 1) >> PRIORITY_SHIFT))
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#endif
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#define GIC_INTR_PRIO_MASK ((UINT8)(0xFFFFFFFFU << PRIORITY_SHIFT))
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/*
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* The preemption level is up to 128, and the maximum value corresponding to the interrupt priority is 254 [7:1].
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* If the GIC_MAX_INTERRUPT_PREEMPTION_LEVEL is 0, the minimum priority is 0xff.
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*/
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#define MIN_INTERRUPT_PRIORITY ((UINT8)((GIC_MAX_INTERRUPT_PREEMPTION_LEVEL - 1) << PRIORITY_SHIFT))
///< 中断最低优先级
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#endif
GICV3
@ GICV3
Definition:
gic_common.h:57
GICV1
@ GICV1
Definition:
gic_common.h:55
GICV4
@ GICV4
Definition:
gic_common.h:58
GICV2
@ GICV2
Definition:
gic_common.h:56
los_config.h
arch
arm
include
gic_common.h
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