47#define OS_SCHEDULE_IN_IRQ 0x0
48#define OS_SCHEDULE_IN_TASK 0x1
50#define PSR_T_ARM 0x00000000u
51#define PSR_T_THUMB 0x00000020u
52#define PSR_MODE_SVC 0x00000013u
53#define PSR_MODE_SYS 0x0000001Fu
54#define PSR_FIQ_DIS 0x00000040u
55#define PSR_IRQ_DIS 0x00000080u
56#define PSR_MODE_USR 0x00000010u
58#define PSR_MODE_SVC_THUMB (PSR_MODE_SVC | PSR_T_THUMB | PSR_FIQ_DIS | PSR_IRQ_DIS)
59#define PSR_MODE_SVC_ARM (PSR_MODE_SVC | PSR_T_ARM | PSR_FIQ_DIS | PSR_IRQ_DIS)
61#define PSR_MODE_SYS_THUMB (PSR_MODE_SYS | PSR_T_THUMB)
62#define PSR_MODE_SYS_ARM (PSR_MODE_SYS | PSR_T_ARM)
64#define PSR_MODE_USR_THUMB (PSR_MODE_USR | PSR_T_THUMB)
65#define PSR_MODE_USR_ARM (PSR_MODE_USR | PSR_T_ARM)
67#define LOS_CHECK_SCHEDULE ((!OS_INT_ACTIVE) && OsPreemptable())
77#define CPU_MAP_GET(cpuid) g_cpuMap[(cpuid)]
78#define CPU_MAP_SET(cpuid, hwid) g_cpuMap[(cpuid)] = (hwid)
173 UINT32 partNo = (midr & 0xFFF0) >> 0x4;
VOID DCacheInvRange(UINTPTR start, UINTPTR end)
Invalidate data cache.
VOID DCacheFlushRange(UINTPTR start, UINTPTR end)
Flush data cache.
VOID FlushICache(VOID)
Invalidate instruction cache.
STATIC INLINE const CHAR * LOS_CpuInfo(VOID)
Get cpu core name.
STATIC INLINE UINT32 OsMainIDGet(VOID)
获取CPU型号,包含CPU各种信息,例如:[15:4]表示 arm 7或arm 9
const CHAR * cpuName
CPU名称